Career Opportunities at PETAiO

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We offer a competitive salary, benefits, stock options, and a chance to be part of something big !

Submit your application at jobs@petaio.com  specifying the position and including your resume. Looking forward to hearing from you soon.

We are looking for ASIC Design Engineers to join our world class team located in Santa Clara, CA.
SSD Controller ASIC design and verification are at the center of PETAiO design and development team. Working together with the Firmware and Technology teams, the ASIC Design team defines the controller architecture and select the ASIC process technology node to develop the most competitive solution meeting and exceeding customers’ requirements to deliver best in class solutions. 

 Responsibilities and Tasks 

• Create architecture and micro-architecture documents
• Responsible for microarchitecture, design and development of IP cores
• Design RTL code using Verilog
• Provide timing constraints, run synthesis, and perform timing analysis 
• Work with Design Verification to validate design and bring up in FPGA
• Develop functional models for architectural validation
• Work with Physical Design team to implement design

Minimum Qualifications 

• Master degree or better in Electrical Engineering or Computer Science
• 5+ years of experience working on ASIC design and  development.
• Experience in micro-architecture and RTL development of complex designs in Verilog.
• Understanding of ASIC design flow including RTL design, verification synthesis timing, ECO, bring up and lab debug.
• Experience with multiple clock domains and asynchronous      interfaces.
• Strong Verilog RTL, C/C++ skills
• Prior experience or knowledge of PCIe, NVME, DDR, ECC and NAND is a highly desirable
• Some Perl or Python scripting experience
• System Verilog would be a plus but not required
• Strong written and verbal communication skills
• Self-starter, good team player, ready to work in a dynamic and rewarding environment 

We are looking for ASIC Verification Engineers to join our world class team located in Santa Clara, CA.

SSD controller ASIC Design and Verification are at the center of PETAiO design and development team. Working close with the ASIC Design and Firmware teams, the ASIC Verification team strives for first time silicon success, a critical factor for products roadmap execution, time to market and customers satisfaction

  Responsibilities and Tasks 

• Participate to the definition of the verification methodology 
• Develop verification test-plans in collaboration with the ASIC and F/W design teams stating from micro-architecture specs, drive system architecture, SSD controller interfaces standard protocols
• Implement the functional coverage metrics in accordance to the verification plan
• Develop and execute verification regression suite, analyze results, enhance test-plan to meet coverage targets
• Identify test failures and interact with ASIC and FW design teams for corrective actions
• Maintain and support the verification platform

Minimum Qualifications 

• Master's degree or better in Electrical Engineering, Computer Engineering, or Computer Science with 5+ years of experience in HDD/SSD storage industry.
• Experience in writing directed and random test-cases
• Understanding of simulation environments using tools like VCS or IUS
• Experience debugging failure logs and waveform using tools such as Verdi/DVE
• Fluent in C/C++ and object-oriented verification languages such as UVM/System Verilog
• Understanding of ASIC block level and soc level verification techniques, such as coverage metrics, directed and pseudo random testing, formal verification, etc.
• Knowledge of various standards, such as DDR3/4, PCIE, NVMe, are a plus
• Strong written and verbal communication skills
• Self-starter, good team player, ready to work in a dynamic and rewarding environment

We are looking for SSD Firmware Engineers to join our world class team located in Santa Clara, CA.
Firmware is the most critical development activity to ensure PetaIO products deliver the required feature and performances. Working very closely with ASIC design, Flash Technology, SSD validation team and key customers, the Firmware team enable the delivery of SSD turn-key solutions to PETAiO customers and partners .

 Responsibilities and Tasks  

• Participate to Front-End High-level and low-level FW design 
• FW Code and design review for cross-check
• NVMe and PCIe SSD FW development and unit test and regression suite
• Participate to Front-End RTL concept design and design review 
• Test and run FW on FPGA, ASIC, SSD bring-up
• Provide SSD turn-key solution for the customers 
• Customer support and on-site debugging

Minimum Qualifications

• Bachelor in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or similar degree
• 3+ years of strong hands-on experience in firmware development including design, development, hardware validation and debugging
• Excellent skill of C/C++, assembly for embedded programming and deep knowledge of CPUs. 
• Strong working knowledge of NVMe and PCIe protocol
• Self-motivated and able to work well with people in the team
• Excellent  written, verbal and communication skills
• Strong      problem analysis and debugging
• Must be willing to overseas travel as needed
• Big plus are Security Protocols, TCG Enterprise, TCG OPAL, Secure Boot, Secure Erase 

We are looking for SSD Firmware Engineers to join our world class team located in Santa Clara, CA.
Firmware is the most critical development activity to ensure PetaIO products deliver the required feature and performances. Working very closely with ASIC design, Flash Technology, SSD validation team and key customers, the Firmware team enable the delivery of SSD turn-key solutions to PETAiO customers and partners .

 Responsibilities and Tasks   

• Participate to Back-end (FTL and NAND) High-Level and Low-level FW design 
• FW Code and design review for cross-check
• Development of FW unit test and regression tests 
• Participate to Back-End RTL concept design and design review 
• Test and run FW on FPGA, ASIC, SSD bring-up
• Provide SSD turn-key solution for the customers 
• Support NAND failure analysis

Minimum Qualifications  

• Bachelor in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or similar degree
• 3+ years of strong hands-on experience in firmware development including design, development, hardware validation and debugging
• Excellent skill of C/C++, assembly for embedded programming and deep knowledge of CPUs. 
• Working knowledge of NAND characteristic and behavior 
• Working Knowledge of FTL and NAND management 
• Well-versed with NAND and NAND Flash Architecture of SSD
• Self-motivated and able to work well with people in the team
• Excellent written, verbal and communication skills
• Strong problem analysis and debugging
• Must be willing to overseas travel as needed

We are looking for SSD Validation Engineers to join our world class team located in Santa Clara, CA.
SSD system level Validation plays a critical role in PETAiO data center products. Working in close collaboration with Hardware, Firmware and Storage Technology, the Validation team ensure PETAiO products are on time to market, deliver the most competitive performances, and meet robustness and reliability targets.

 Responsibilities and Tasks

• Responsible for the definition, implementation and execution of the SSD Validation Test Plan. 
• Manage interactions with HW, FW and Flash technology teams on all aspects of validation to ensure that all issues are detected and resolved with a rapid and satisfactory solution.
• Define and implement test plans to validate functionalities, features and performances.
• Support design and development engineers to improve and optimize SSD performances, robustness, and reliability.
• Work in close collaboration with third party validation platforms and tools providers to achieve most proficient and productive usage.
• Enhance regression test scripts to improve validation test coverage and efficiency.
• Manage validation computational resources and regression scripts for 24x7 system utilization

Minimum Qualifications

• Master degree or better in Electrical Engineering, Computer Engineering, or Computer  Science with 8+ years of experience in HDD/SSD storage industry.
• 3 or more years of experience in developing complex SSD      validation test suite on proprietary or commercial validation system      platforms like Oakgate
• In-depth knowledge of NVMe standards including the latest revisions. 
• Strong programming and scripting language skills is required. 
• Detail oriented, analytical, process savvy, yet flexible and adaptable to fast-paced and dynamic environment.
• Experience working in cross-functional teams’ environment
• Strong verbal and written communication skills
• Self-starter, good team player, ready to work in a dynamic and rewarding environment 

We are looking for SSD System Architects to join our world class team located in Santa Clara, CA.
SSD System Architect plays an essential role in PETAiO data center products. Research and develop in cutting-edge Storage Technology. Work closely with ASIC and Firmware teams. The SSD ystem Architects ensure PETAiO products are always the best in class.

 Responsibilities and Tasks

• Design and implement NAND management algorithms for SSDs
• Develop a NAND characterization platform to facilitate NAND management algorithms research
• Develop an SSD simulation model to facilitate algorithm research
• Design future generation error control coding algorithms for NAND flash (knowledge of LDPC, BCH codes preferred)
• Collaborate across ASIC and firmware teams to deliver successful products

Minimum Qualifications

• MS in Electrical or Computer Engineering; PhD is a plus
• Excellent programming skills in at least one of the software languages, e.g. C/C++, Java, Python
• Excellent analytical skills for formulating the real problems and providing solutions
• Fast learner with good communication skills
• Must be proactive and a strong team player
• Knowledge of NAND and SSD (preferred)
• Knowledge of signal processing and coding theory (preferred)